Semiconductor integrated circuits often incorporate hundreds of thousands of semiconductor elements on a single chip. Logical functions are typically separated by sequential elements, such as flip-flops, which define clock boundaries within individual signal paths.
It is common to convert at least some of the sequential elements with “scannable” elements that assist in testing the integrated circuit after fabrication. One common testing methodology is referred to as “scan testing”. Scan testing can be implemented, for example, by converting selected sequential elements into scannable elements by adding extra logic and a multiplexer. Each scannable element selects data from a normal data input or a test data input based on a test enable signal. The scannable elements are connected together by forming a scan chain, wherein the output of each scannable element is connected to the test data input of the next, subsequent scannable element in the chain.
With integrated circuit designs becoming larger and larger, power consumption within a particular design becomes more and more important. With current scannable elements, the logic that is added along the scan path to implement scan testing includes logic that toggles during the normal, functional data flow mode. As a result, the test logic that continues to switch and consume power although the logic is not functionally used during normal operation.
Similarly, during scan-shift when vector are being scanned through the scan chain, functional gates that are not used during scan-shift continue to toggle and consume power. This extra power consumption can become high, especially since the scan-shift frequency is typically set as high as possible to reduce the test time. As a result, the maximum power-consumption of a device can occur during scan-shift.
Improved sequential devices are therefore desired that are capable of consuming less power.